The present invention relates to a semiconductor device such as a solid-state imaging device, a method of manufacturing the same, and an electronic apparatus such as a camera with the solid-state imaging device.
Solid-state imaging devices include an amplification type solid-state imaging device of which an illustrative example is a MOS image sensor such as a CMOS (Complementary Metal Oxide Semiconductor). In addition, solid-state imaging devices include a charge-transfer type solid-state imaging device of which an illustrative example is a CCD (Charge Coupled Device) image sensor. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors have widely been used as solid-state imaging devices mounted on mobile apparatuses such as portable phones with an attached camera or PDAs (Personal Digital Assistant), in terms of low power voltage, power consumption, and the like.
A MOS solid-state imaging device includes a pixel array (pixel region), where a plurality of unit pixels each including a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors are arranged in the form of a two-dimensional array, and a peripheral circuit region. The plurality of pixel transistors are formed as MOS transistors and include three transistors of a transfer transistor, a reset transistor, and an amplification transistor, or include four transistors, including a selection transistor.
In the past, various MOS solid-state imaging devices were suggested in which a semiconductor chip in which a pixel array arranging a plurality of pixels is formed and a semiconductor chip in which a logic circuit performing a signal process is formed are electrically connected to each other to form one device. Japanese Unexamined Patent Application Publication No. 2006-49361 discloses a semiconductor module in which a back-illuminated image sensor chip including a micropad in each pixel cell and a signal processing chip including a signal processing circuit and micropads are connected to each other by a microbump.
International Publication No. WO 2006/129762 discloses a semiconductor image sensor module in which a first semiconductor chip including an image sensor, a second semiconductor chip including an analog/digital converter array, and a third semiconductor chip including a memory element array are stacked. The first and second semiconductor chips are connected to each other by a bump which is a conductive connection conductor. The second and third semiconductor chips are connected to each other by a through contact penetrated through the second semiconductor chip.
As disclosed in Japanese Unexamined Patent Application Publication No. 2006-49361, various techniques for combining different kinds of circuit chips such as an image sensor chip and a logic circuit performing signal processing have been suggested. In techniques according to a related art, functional chips in a nearly completed state are connected to each other by forming a through connection hole or via a bump.
The inventors have recognized a problem with bonded semiconductor chip sections where pair ground capacitance and adjacent coupling capacitance occur as parasitic capacitance. The pair ground capacitance is parasitic capacitance occurring between a wiring and a semiconductor substrate, for example, with a ground potential. The adjacent coupling capacitance is parasitic capacitance between adjacent laying wirings or adjacent conductors. While the counter ground capacitance may be cleared when a power source is enhanced or a buffer circuit is provided to allow current to flow, the adjacent coupling capacitance may not be cleared due to interference between adjacent lines.
This problem with the parasitic capacitance may also arise in a semiconductor device in which semiconductor chip sections each including a semiconductor integrated circuit are bonded to each other and both the semiconductor chip sections are connected by a connection conductor and a through connection conductor.
It is desirable to provide a semiconductor device such as a solid-state imaging device reducing parasitic capacitance to achieve high performance and a method of manufacturing the semiconductor device. It is desirable to provide an electronic apparatus, such as a camera, which includes the solid-state imaging device.